1. Field of the Invention
The present invention is related to data processing systems and more specifically to an in-circuit emulator which minimizes the likelihood of slip between the time a microprocessor generates a candidate for a break event and the time the microprocessor is instructed to perform the break, without missing breakpoints.
2. Prior Art
An in-circuit emulator (ICE) duplicates and imitates the behavior of a chip it emulates by using programming techniques and special machine features to permit the ICE to execute micro code written for the chip that it imitates. In the aboveidentified Hinton et al. statutory invention registration H1291, a microprocessor is disclosed in which several instructions may be executing at the same time in a pipelined manner. In this microprocessor the execution is so fast and so many instructions are executed in such a short period of time, that an emulator may be unable to stop on the instruction which generated an event that caused a break in the operation of the microprocessor under test. This situation is called slip. It means that one or more instructions are executed after the instruction which generated the event before emulation is terminated in response to a break. Slip allows more instructions to execute after an on-chip Instruction Pointer (IP) match is satisfied before a break is initiated. For the emulator function to perform satisfactorily, this slip condition must be minimized.
Copending patent application Ser. No. 07/985,563 provides an apparatus that will control a number of on-chip break mechanisms externally using only a single input pin. The emulator includes an instruction pointer counter (IP counter) and a break logic connected to the IP counter. The break logic has an arm input and is capable of matching the IP counter to an instruction execution address.
It is not feasible to place all of the logic analysis capability of a full featured emulator on the chip because of die area constraints. This invention allows the logic analyzer to be split into two segments: (1) a large complex segment with many levels of arm logic, disarm logic, counters, comparators, etc. located off the chip, and (2) a small, simple, fast segment with one layer of arm logic which resides on the chip. The two segments are connected serially, the off-chip segment preceding the on-chip segment. The invention minimizes the likelihood of slip to one region where the off-chip analyzer arms the on-chip analyzer, instead of creating a dead zone.
Once a cluster is armed, an instruction pointer (IP) match from the IP marchers that occurs after the cluster is armed results in a no-slip break, because as soon as the cluster fires in response to a break event, it having been previously armed, the emulation stops immediately. However, if an IP match happens between the time the break event occurs and the arm signal arms the cluster, a dead zone of many clocks occurs. In this situation it is possible for a break to be missed. The present invention changes the region of dead zone into a region of slip.
It is therefore an object of this invention to provide an in-circuit emulator in which the likelihood of slip between the time a candidate for a break event occurs and an arm signal arms the emulator to detect the break is minimized, without missing breakpoints.